Spurious Charge

When using CCDs for applications where binning of more than 4 pixels is required, care has to be taken to design the CCD driver circuit to avoid the generation of spurious charge. During the design phase and, most of all, during the final camera test and calibration procedure, precaution is taken to deliver all cameras tuned to generate no additional spurious charge.

How is spurious charge generated ?

• Spurious charge is generated on the leading edge of the drive clock which is when the phase assumes the non-inverted state and holes are forced back to the channel stop regions. The falling edge of the drive clock has no influence on spurious charge generation in CCDs.
• Spurious charge increases exponentially with clock rise time and voltage swing, sending holes back to the channel stop. A fast moving, high amplitude clock increases impact ionization.
• Spurious charge increases with clock width or with the escape from the interface resulting in more spurious charge.

How to reduce spurious charge ?
There are three methods used in the our cameras to reduce the shot noise produced by spurious charge to negligible levels.

• One method is to optimize the rise time of all drive clocks, to allow the holes to go back to the channel stop regions as slowly as possible. This is accomplished by adding a carefully matched R-C network at the output of each CCD clock driver that matches the capacity of the CCD gates and the parallel clock width.
• All horizontal clocks of the CCDs are operated in non-inverted mode since dark charge in the register is not important.